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New opportunity as Senior UVM Verification Lead – working for an exciting semiconductor scale-up company, based in the beautiful setting of Lausanne, overlooking lake Geneva.
You will be working on the latest developments in high-speed communications, on products such as: SerDes, DSP, ethernet and PCIe.
As Senior UVM Verification Lead, you will perform a hybrid role – with responsibilities for leading a small team, as well as maintaining hands on control of verification of ASIC IP products.
- Act as verification lead on projects
- Provide technical leadership & mentoring
- Prepare design verification plan based on design specifications
- Plan and schedule projects , assign and track tasks for team members
- Develop design verification methodologies and implement standard debug flows
- Participate in design reviews
- Maintain design verification environment and track & close design bugs
- Work with designers in verification and validation of circuit designs
- Utilise the latest techniques, tools, and technologies for design verification activities
- Excellent communication skills, strong team player
- Good scripting techniques, experience with regression setup & management – TcL, pery, shel, python, c
- Deep understanding of simulation and verification environments, including debugging techniques
- Experience with Gate Level Simulation flows and debug.
- Strong knowledge on Metrics-driven verification (incl. verification planning and coverage closure)
- Experienced with testbench development using the latest methodologies
- Experience with 3rd party VIP usage and test development (a big plus)
- Bachelor’s degree in electronics or micro-electronics or similar field
- 7+ years’ experience in the semiconductor industry
- Experience in leading and managing a team
- Proven track record in verifying complex designs (preferably in high volume applications)
- Skilled in trade-offs between quality and schedule
- Experience in constrained random testbench development
- Familiarity with SerDes and high-level protocols (e.g., PCle, USB, DP) would be advantageous
- Extensive digital verification background with some UVM experience, system verilog etc.
Visa sponsorship can be offered
Please contact Rob Click here to contact this recruiter Resources for more information